The subject invention generally relates to a system for directly writing circuit patterns with a focused laser beam and, more particularly, to interconnecting integrated circuit chips which are not accurately placed by first identifying the actual position of each chip and subsequently adapting interconnection and via patterns to conform to the actual chip positions. The term "artwork" is often used and refers to such pattern in the form of a database which describes interconnect structure and via hole structure for providing interconnects between electronic components. The modified artwork provides information to drive a focused laser beam under computer control to directly write circuit patterns in metallization and photo resist. The present invention in related to a packaging system and method in which polymer film overlays are provided with metallization patterns as a means for configuring an integrated circuit chip or chips in an operating arrangement.
The interconnection of pre-packaged circuit chips has been a principal means for the assembly of many electronic systems. In one such method, "the wire wrap method", sockets with wire wrap pins are provided and logic chips to be interconnected are placed in these sockets. Subsequently, interconnections are provided by wrapping wires around wire wrap pins according to a wire list. This can be done by automatic or manual machinery. The major drawback of wire wrap is the length of time required to wrap a single circuit board. This precludes this method from being economic for all but prototyping applications. In addition, wire wrapped boards cannot be checked for accuracy of wiring, both in interconnection accuracy and for shorts, except through the use of expensive, dedicated machinery. Also, wire wrap provides a relatively low performance interconnection since conductor runs are relatively long and since they also suffer from high capacitance loading effects. Also, once chips have been installed on a wire wrap board, it is difficult to partition the board for simple tests. Thus testing to the required high degree of functional assurance generally requires complex and time consuming testing apparatus. Finally, wire wrap prototyping boards are expensive because they contain a large number of holes and each wire wrap socket must supply long pins for wire wrapping.
Printed circuit boards are another method of interconnecting pre-packaged electronic circuit chips. A printed circuit board typically comprises copper runs adhered to an epoxy/glass fiber base substrate or the like. Packaged chips are mounted on the substrate and package pins are soldered to runs on the printed circuit board. In terms of prototyping, the time from completion of the circuit definition until populated boards (that is, boards with chips) are received can be quite long. Layout of printed circuit boards, if done by hand, can require two weeks to a month for a fairly complicated circuit board containing one hundred to two hundred chips. Even with computer aided layout, the amount of computer time required to route the board is substantial for a complicated board. In addition, complicated boards typically require multiple circuit layers which makes design and fabrication of printed circuit boards an even more time consuming process. A typical short turn around time can be on the order of two weeks. In addition, special tooling must be provided in order to test that all the connections are made on the board and that no undesired short circuits exist. At this point it is still necessary to populate the board with chips and to solder them in place. Chip population is generally done in different plant locations than board fabrication because a large number of chips must be kept in inventory and are specific to the needs of a particular operating department, while board fabrication is more generic in nature. The problem of testing the finished assembly is the same as with a wire wrap method in that a fully interconnected assembly generally requires a large array of complex test vectors (sample input patterns designed to exercise particular chip functions) in order to derive a high degree of assurance that the system will work under all desired conditions.
A gate array is also a solution to the problem of providing an electronic chip system. A gate array is primarily a medium to high volume device. In a typical gate array, arrays of P-channel and N-channel transistors are fabricated in an array structure on integrated circuit wafers. These circuits are generally completely fabricated with the exception of the last metallization step. Logic designs are achieved by custom connecting the P-channel and N-channel transistors with the last metallization layer. This method makes relatively efficient use of chip "real estate" and typically utilizes computer aided layout directly from circuit definitions. However, time is required to fabricate masks for the last metallization step and to finish the processing of the wafers. A typical time for the steps of automatic layout, mask generation and chip fabrication is generally at least two weeks. At this point, thousands of chips can be relatively easily fabricated, but thousands of chips are generally not required for prototyping quantities and for many applications. To further complicate the problem, complete systems require custom testing by the vendor of the gate array with the test vectors and conditions developed and supplied by the circuit engineer. This must be done before the chips can be packaged. This means that the circuit engineer must carry out a sufficiently detailed simulation to develop a set of qualification test vectors. Further testing must be accomplished after prototype chips arrive at the circuit engineer's site. While simulation can greatly decrease the risk of design errors in the chips, it does not cover the operation of a chip in an electronic system substantially similar to its operating environment. Generally, faults will be found and updates will be necessary and the requirement for additional prototypes with more changes will be created. This process is both costly and stretches the time to completion of a project substantially because each iteration generally requires at least two weeks. In addition, a single gate array cannot provide all the structures necessary for a complete electronic system. For example, voltages and current may not be compatible at the interface level and may require addition of bipolar devices for analog-to-digital conversion at the input and digital-to-analog conversion at the output. Also, many systems require some form of memory. This means that the gate array would necessarily require an additional printed circuit board to interconnect the memory or interface devices.
A programmable logic array can be used to provide an electronic system economically in low volume for some applications. The major disadvantage of logic arrays is that they make inefficient use of silicon because the logic array must provide for all possible Boolean functions in "AND/OR" configurations. In those few applications where this type of Boolean logic is required, the logic array can be programmed for the desired Boolean functions. Most systems, however, require a large number of logic arrays to achieve the desired function and this is not economical except possibly for the very first prototype.
Fully customized integrated circuits can generally provide about two or three times the functionality available in the same area from a gate array, but the processing cost and non-recurring cost is substantially increased. Circuit layout involves all layers of the chip. Three month turnaround times are typical for the processing associated with a fully custom integrated circuit chip. Test vectors and probe cards are also unique to each application specific integrated circuit (ASIC) situation. This means that substantial number of chips must be involved before the fully custom chip is economical. As a rule of thumb, volumes over ten thousand units per year are generally required.
In the packaging of very large scale integrated (VLSI) circuit devices, a great deal of space is taken up by mechanisms for interconnecting one chip to an adjacent device. This makes the packaging of integrated circuit devices and electronic components based thereon larger than necessary. As a result of this, many individuals are involved in the development of so-called wafer-scale integration processes. However, efforts expended in these directions have generally tended to be limited by the problem of yield. Because a certain number of chips or dies on a wafer are often found to be defective, the number of wafers that are produced that are completely usable is generally lower than is desired. Furthermore, there still exists the problem of interconnecting the various chips on a wafer and the concomitant problem of testing a large system, such as results when a number of highly complicated individual integrated circuit components are interconnected. Accordingly, it would be very desirable to be able to construct wafer scale integrated circuit packages from individual, easily testable integrated circuit chips. It is to this end that the present invention is directed.
The invention described herein also solves a slightly different problem with the same method and structure used to solve the wafer-scale integration problem. In present day electronic systems, the primary components are usually readily available. These components include random access memory (RAM) and microprocessor chip family sets as well as analog-to-digital and digitial-to-analog conversion chips. In present day systems, these primary components are interconnected using transistor-transistor logic (TTL). TTL logic refers to a set of functional blocks generally referred to as the 7400 series and is described in the handbook The TTL Data Book for Design Engineers published by Texas Instruments, Inc. This function of interconnecting, buffering and tying together the primary components of the system is generally referred to as a "glue logic function". For example, in present day integrated circuit boards, one often finds certain standard functional chips surrounded by a plurality of custom interconnected integrated circuit chips in familiar dual in-line packages (DIP packaging). It is these numerous small surrounding chips that provide a "glue function". In future systems, the glue logic function may be provided by gate arrays and custom chips where a single chip replaces a large number of TTL chips. This leads to several problems. The first is that the number of pins in the custom glue chip can be quite high. In addition, all of the primary components are immediately available. In the past, TTL was also immediately available and system interconnection could commence immediately on receipt of a given design. However, a time discontinuity now exists in which the primary components are available, but the custom glue logic takes many weeks to fabricate. The invention described in copending application Ser. No. 912,457, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique Test Capability" uses a generic glue logic chip which can be used in place of a large number of TTL logic chip.
In a different process seeking to achieve some of the same objectives as the present invention, semiconductor chips are mounted on a substrate, and a layer of material such as polytetrafluoroethylene (PTFE) is pressed over the tops of the chips and around the chips so that the chips are completely encapsulated in this layer. Holes are etched in the encapsulating layer corresponding to pad positions on the chips. Metallization is applied and patterned to form interconnections. However, the present invention is significantly different from such processes for the following reasons. In the process just described, known as semiconductor thermodielectric processing (STP), the chips are completely embedded in PTFE material so that no overlay layer as such exists. This makes it impossible to repair an assembly since the chips cannot be removed. Even if a chip could be removed, the remaining chips would still be encapsulated in the PTFE material and there would be no way to install a replacement chip. In addition, there is no provision in the semiconductor thermodielectric processing method for a removable metallization layer which is selectively etched, thus protecting the underlying circuit while assuring complete removal of the metallization layer. In addition, the semiconductor thermodielectric processing method faces two other problems. First, by encapsulating chips in a polymer, a high degree of stress is created by difference in thermal expansion coefficients. Second, the thickness of the polymer over the top of the chips is governed solely by the thickness of the chip and the tooling which encapsulates the chips. Variations in chip thickness lead to variations in the thickness of the polymer over the chip.
As described in more detail in, for example, copending applications Ser. No. 912,456, entitled "Multichip Integrated Circuit Packaging Configuration and Method" and Ser. No. 912,458, entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer", a multichip integrated circuit package is produced by arranging a plurality of individual integrated circuit chips on a common substrate and then covering the chips on the substrate with a polymer film overlay layer or layers. The via holes are formed and metallized interconnections between the pads of the individual chips are provided. However, by itself, this packaging technique is highly dependent on the precise and accurate placement of the chips on the substrate. What is needed, especially for automated packaging of integrated circuit chips, is a procedure which is less dependent on the highly accurate placement of the chips on the substrate.
In one embodiment of the present invention, a polymer film covers a plurality of integrated circuit chips adjacent to one another on an underlying substrate. Furthermore, the polymer film provides an insulative layer upon which a metallization pattern for interconnection of individual circuit chips is eventually deposited. The method of disposing a polymer film over a plurality of integrated circuit chips affixed to an underlying substrate is described in copending application Ser. No. 912,458, entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer". The invention disclosed therein solves significant problems with respect to high temperature processing and the requirement for excellent compliance of a plastic material to an irregular surface. The chips include interconnection pads for connecting to other integrated circuit components or for connecting to other parts of the same chip. Via openings or apertures in the polymer dielectric layer are aligned with the interconnection pads. The pattern of interconnection conductor is disposed on the overlying polymer film so as to extend between at least some of the via openings so as to provide electrical connections between various parts of a chip or between several chips. The method for producing via holes in polymer dielectrics for multiple electronic circuit chip packaging is described in copending application Ser. No. 912,455, now U.S. Pat. No. 4,714,516, issued Dec. 22, 1987 and entitled "Method to Produce Via Holes in Polymer Dielectrics for Multiple Electronic Circuit Chip Packaging".
Metallization is preferably provided by sputtering a one thousand angstrom thick layer of titanium, followed by a one micron thick layer of copper over the polymer film and into the via holes. The metallization is preferably patterned by spraying or spinning a coating of photoresist on the copper surface, drying for about one half hour at approximately 90.degree. C. and exposing the positive resist material with a scanned ultraviolet (UV) laser beam under control of computerized artwork. A preferable photoresist material is Dynachem OFPR 800 photoresist.
To maximize the operating speed of the final system, interconnection from one chip to another is preferably accomplished with a minimum of capacitative loading and a minimum of interconnect length. Capacitative loading tends to slow down signal transmission such that high speeds attained on the chip cannot be maintained in communicating from one chip to another. Interconnection length between chips also contributes to propagation delay due to greater capacitative loading effects in the dielectric medium due to circuit length and also due to a self inductance of the interconnection circuit. The metallization is patterned to form very fine lines and spaces, typically under 1 mil in line width and 1 mil in line spacing. Copending application Ser. No. 912,456, entitled "Multichip Integrated Circuit Packaging Configuration and Method" describes the ability to interconnect chips placed edge to edge because the metallization pitch is much finer than the pad spacing.
The lithography system adapts to inaccurately placed chips by modifying database artwork patterns representing an ideal interconnect pattern so as to accommodate the actual position of integrated circuit chips. Commercially available chip placement devices are not sufficiently accurate to position chips with the resolution capability of a laser scan system. In accordance with this invention, a method is disclosed for modifying artwork representing an ideal interconnect pattern to accommodate the actual position of the integrated circuit chips. The four major steps required are: generating artwork patterns for the ideal case, determining the actual positions of each integrated circuit component, modifying the artwork to match the actual chip positions, and using the modified artwork to produce the desired effects in an adaptive lithography scanning system.
Artwork is generated for the ideal positioning of integrated circuit chips using a computer-aided layout system. This computer-aided design system is provided with a first data base containing information as to the integrated circuit chips size, their ideal position and orientation if that is user specified, the location of connection pads on each integrated circuit chip and a list of the required connections among the various connection pads on the various integrated circuit chips. The computer-aided design system then provides a layout for the chips on the substrate and the printed circuit metallized conducting paths in the form of a second data base. The various conducting paths may preferably be stored in vector form as a series of straight line segments each specified by its starting and ending points. All interconnect, via hole definitions, and chip boundary definitions are stored in a file. The chip boundary definitions include an outline of a chip including its ideal position and orientation and an outline of the extent to which the chip can be misplaced. The actual positions and orientation of the integrated circuit components are determined from connection pad and chip outline information. Ideally, this process is performed automatically by using a charge-injection device (CID) camera and an image recognition technique to align each circuit chip and calculate offset and rotation information. In the process actually implemented and described hereinafter, the process is partly manual. More specifically, the substrate is aligned on the x-y table in both location and rotation according to fiducial marks on the substrate. The monitor for the CID camera is equipped with a bull's-eye or cross-hair pattern on the center of the screen. When the fiducial mark on the substrate which corresponds to the mirror zero position is near the bull's eye, the x and y position counters are reset to zero. The computer then supplies pulses to x and y stepping motors to step to the ideal position of the upper right hand pad of the integrated circuit chip. A mouse connected to the computer is used to move the image of one pad of the actual chip directly under the cross-hairs. The difference between the actual position and the ideal position is recorded. Then the computer steps the x-y table to the expected position of a pad on the opposite side of the integrated circuit chip, making the assumption that the chip is not rotated from the ideal position. The mouse is used again to position the image of the actual pad directly under the cross hairs. Again, the difference between the actual position and the ideal position is recorded. The offset and rotation of the actual chip is then recorded from the results of the two operations. The computer then goes to the next chip in sequence and determines its offset and rotation and this process is repeated until the offset and rotation of all the chips have been recorded. The information determined during this step is stored in a database which defines the chip positions. The ideal artwork is modified to match the actual chip position. All of the interconnect patterns and associated via holes are modified to incorporate the offset and rotation associated with each integrated circuit chip. The modified artwork is used to drive the adaptive lithography scanning system. The modified artwork is used to supply the commands for positioning the x-y table and to supply data to the high speed processor for driving the adaptive lithography scanning system and for modulating the laser beam so that a modified printed circuit pattern can be printed on the substrate.
The structure of the adaptive lithography system includes a primary laser beam path which starts from an Argon ion laser which is adjusted with optics to provide ultraviolet (UV) output. The laser provides a single beam which may be divided, with beam splitting optics, into as many beams as are required. The laser beam is then passed through an acousto-optical modulator which deflects the beam when a high frequency signal is applied. A plate with an aperture is positioned approximately one meter from the output of the modulator. The non-deflected beam is stopped by the plate and the deflected beam passes through the aperture.
The deflected beam is expanded to the desired diameter laser beam with a beam expander. The expanded beam is directed to a galvanometer driven scanner which has a (9-millimeter) diameter scanning mirror and an internal sensor which is coupled with a servo-amplifier to accurately position the mirror. The scanned beam is focused onto a substrate with a conventional plano-convex lens. A second laser is used to accurately determine the position of the scanning mirror at all times during the scan. The second laser beam is passed through a graticule and focused on a PIN diode detector.
A CID camera with a microscope objective is mounted to observe the area on the substrate where the laser beam focuses. Precise correlation between the laser beam position and the image of the CID camera is obtained. The substrate is positioned on a precision x-y table, which is positioned by precision screws attached to separate motors. The CID camera is connected to a video subsystem which drives a television display.
A microcomputer, such as a MS-DOS personal computer (PC), manages the process and dataflow. An input/output board connects special control electronics which manage the motion of the x-y table to the PC. The image data from the CID camera is sent through an interface board to a high speed processor which generates bit map patterns of the artwork stored in vector form. The control electronics for the adaptive lithography system can be divided into three major sections which are: x-y table control, mirror scan control, and laser data control. Circuitry is included which assures that the x-y table is in exact synchronism with the position of the scanning mirror. The lithography system operates by converting a file stored in rectangular vector form to a controlled flow of data which modulates a laser beam in synchronism with its position on the substrate to be exposed.
The system can be expanded to achieve higher throughput rates at a substantial savings by duplicating only essential parts of the device. The system can be duplicated as many times as required to obtain the desired throughput rate. The acousto-optic modulator, the expander, the scanner, and the focus lens as well as the alignment laser and the graticule must be duplicated. The x-y table, the CID camera, the PC, the laser and other equipment need not be duplicated.
The adaptive lithography system according to the present invention is particularly attractive because it requires few processing steps. Also, the time to produce photomasks and the yield and deterioration problems are eliminated. If desired, the direct writing system is able to customize each circuit produced.